High speed data communications are susceptible to noise, which results in corruption of the data during transmission. Forward error correction (FEC) schemes have been developed to enable receivers to detect and correct errors in the data they receive. Typically, stronger FEC schemes are used for faster data rates. A “stronger” FEC scheme is one that can detect and correct a greater number of bit errors in a block of data than a “weaker” FEC scheme.
The communications industry generally has progressed over time to using increasingly fast rates. For example, Ethernet connections with single lane rates of 25 Gigabit per second (25 Gbps) are currently being used within data centers. Recently, 50 Gigabit per second (50 Gbps) single lane rates have become more prevalent. In evolving networks, the data rate for all communications does not switch over from a slower data rate to a faster data rate instantaneously. Instead, evolving networks need to support data communications at multiple data rates simultaneously. To support multiple data rates, receiving equipment can be configured to support multiple different FEC schemes used for the transmissions at each of the data rates. For example, the FEC scheme for serial links carrying data at 50 Gbps per lane is stronger than the FEC scheme for serial links carrying data at 25 Gbps per lane. To accommodate multiple FEC schemes, existing equipment includes dedicated FEC decoders for each encoding scheme used in the network—e.g., a receiving device includes one decoder for 25 Gbps communications, and another decoder for 50 Gbps communications.
A typical FEC decoder used for 50 Gbps lane rates consumes approximately 1.9X the silicon area (i.e., chip size) compared to the silicon area consumed by a typical FEC decoder for 25 Gbps lane rates. Hence, with two dedicated, separate FEC solutions, the total silicon area is 1.9X+X=2.9X. In enterprise data center applications, in which each switch or router supports multiple ports each with its own set of decoders, reducing the silicon area per port can have large impact on chip size and static power consumption.